1. Field of the Invention
This invention relates to programmable logic devices, and more particularly to a programmable logic device utilizing sense amplifiers which may be powered down to eliminate the current draw from the unused sense amplifier.
2. Description of the Prior Art
Programmable logic devices are known in the prior art and an example of one such devices is illustrated in U.S. Pat. No. 4,833,646 issued to John E. Turner on May 23, 1989 and assigned to the assignee of the present invention. The Turner patent is incorporated herein by reference in its entirety.
As for the background, attention is directed to FIG. 1 herein wherein a highly simplified, partial diagram of a programmable logic device is illustrated. Programmable logic device 1 is illustrated in highly simplified form in FIG. 1, and includes programmable AND 5 array 2, sense amplifiers designated SA1-SA6 and a six input OR gate 3. Logical inputs A, B and C are illustrated, although in a commercial programmable logic device typically a greater number of logical inputs would be utilized. Through the use of buffer inverters 5, 6 and 7, logical inputs A, A, B, B and C, C are connected to array lines 8-13 using respectively. Product term lines PT1-PT6 may be selectively connected to array lines 8-13 using the memory cells which are located at the intersection of the array liens and product term lines, these memory cells being indicated by an X. The memory cells utilized in programmable AND array 2, may be of the type illustrated in the above-identified Turner patent. By programming a memory cell at the intersection of an array line and a product term line, the logical inputs to the programmable logic device are provided to the product term lines corresponding to the intersection between the array line and the product term line as programmed. A sense amplifier is connected to each product term line and is used to sense the programmed/unprogrammed state of the memory cells connected to the product term line. Using circuitry of the type illustrated in the Turner patent, the state of each memory cell may be determined. Sense amplifiers SA1 through SA6 may be of the type illustrated in FIG. 5 of the above-identified Turner patent. The outputs of sense amplifiers SA1-SA6 are inputs to OR gate 3, and output terminal 15 of OR gate provides the logical sum output indicating the result of logical input signals to the programmed logic device 1.
In the prior art programmable logic device 1, if a product term is not going to be used to implement the logical function programmed for the logic device, that is the logical input to OR gate 3 will always be in the low condition for that product term, the sense amplifier associated with that product term is nevertheless retained in the circuit and draws current. Thus in a high density programmable logic device if there are a significant number of unused product terms, then a correspondingly significant number of sense amplifiers would remain operable and the current consumption would be unnecessarily high. For example, in programmable logic device 1, if product term PT1 is not used in the logical function being implemented, to maintain the output of sense amplifier SA1 low, the true and complement cells for product term line PT1 are all programmed to insure that the output of sense amplifier SA1 will always be low. Accordingly, sense amplifier SA1 even though not utilized in the logical function will always be in operation and continue consuming a current.